Loading new input :)

[Newbie_barbie]

hi
I'm new to this site and to vhdl coding as well. hope I get some help..
I have to design a system which loads series of input and store it into a register. The input has to be accepted through same pins of FPGA.
For example
My 1st input data(4 bits) is 1010, this data gets stored into reg1
2nd input data is 1111, this has to get concatenated with reg1 previous contents.
3rd input data is 0101, this has to concatenate with reg1 previous contents and so on.
I thought of using for loop but read somewhere that for loop isn't synthesizeable so please help me in writing the code. I need help as soon as possible.
I have a doubt too--
How will FPGA accept data through same pins one after the other. ??????
Regards

 

[TrickyDicky]

I suggest you read up on digital design. VHDL is NOT a programming language, it is a hardware description language. You need to understand the hardware before you can write any VHDL code.

So get a peice of paper and before writing the code, draw the circuit you're trying to create. If you cant do this - then you have a lot of reading/ learning to do.

 

[rberek]

To further focus your reading, you are going to have to develop some sort of register interface protocol. Normally, the FPGA would have to receive an address (all your data isn't being stored in reg1 is it?), data, and a read/write pulse at a minimum. Your description is not very detailed, but since you describe writing part of a register, you would also need nybble enable signals. Then you can write code that will monitor those signals and use the address and nybble enables to place the 4-bit data in the correct location of the correct register.

That is what you need for a generic random access synchronous register interface. Without more details not much more can be said about it.

r.b.