Re: Help needed in design of a 6 transistor SRAM
The SRAM designs I've seen, which are pretty old now,
used a column precharge and the bit cell would discharge
it, or not, when connected. This made the operation low
power, but the capacitance needed to be less than would
upset the bit when attached by the switch (or, core pair
sized up to accommodate the line capacitance). I doubt
anyone wants a DC load on a read line so this scheme may
still dominate. In which case, your schematic needs to
represent a somewhat realistic C on the true and complement
lines.
Your sense amp might simply be a cross-coupled inverter pair
that is attached across those lines, and the charge difference
on the true / complement Cs will be regeneratively gained up
to a logic level. This needs to be synchronized, the precharge
and the sense amp and the latching of result, a mini state
machine. You don't want precharge to be any longer than
necessary, since it's a slug of power wasted into the sense
amp, but long enough to charge Cline (varying w/ layout,
processing, temp, Vdd, etc.).