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I designed a 6T SRAM cell by referring to CMOS Digital IC Analysis and Design by Kang and Leblebici. Digital Integrated Ckts by Jan Rabaey might also be useful. Chk out the attached material. Might be of use.
you can use a minimum sized 6T cell (8T for dual port) in a lot of cases if your speed constraints are not so tigth (say up to 200Mhz),though you will of course need to simualte to check that the cell contents will not flick over once you have done an operation.
Your parasitic caps of the data lines will also be critical and you will to take this into account at the schematic stage.
Expect read/write cycle times to increase dramacitcally once you simulate the extracted layout ... eg I designed once for Tread=6ns and ended up with 10-11ns once the layout was simulated ...
might sound a bit off topic here, but in case of a student project, can I just do simulations for one sram layout extracted cell and then extrapolate the rsults for an array. If no, what greater design experience would I get or problems would I face in the entire array.
Added after 1 minutes:
please tolerate once more, I am not much aware of how edaboard works
Please be informed that,
you may design SRAM with 6T by refering any reference book, but testing/simulation for write/read/idle cycle of SRAM is not that easy as we expected, for that you are required additional circuits to be attached together with 6T SRAM. Those additional circuits are precharge circuit (4T),sense amplifier (4T), and equalizer(1T) and 2 chargeing capacitors.
Hey everybody....i found all of ur post quite helpful n wish to share my problem...i have a project on SRAM 6t cell...i have to calculate biitline measurements and for that I have to calculate BL curent...i tried but m unable to...
So...is this additon of sensing amplifier and capacitors etc is really neceassary in wat m doing bcz i hv nt yet aded them...pls help...m new to hspice n m trying to learn it...