limitations and solutions in low voltage design of adc

[userss]

low voltage adc

I need sources about limitations and solutions in low voltage design of A/D converters. Can you give me suggestions?

Thanks

 

[userss]

Low voltage adc

??

 

[rfsystem]

Re: Low voltage adc

I'll give you an example about the limitations.

For instance if you use a charge-based processing for the ADC which is a cyclic, pipeline or charge-redistribution you try to maximize to the given supply voltage.

The cap size should be ultimate defined by the noise

Vn^2=k*T/C

If you can use a fraction "a" from the supply and set the noise voltage to 3*sigma=1LSB then the cap should be

C>k*T/(a*Vdd*/(3*2^n))^2=774fF for a=0.75, Vdd=1.2V, n=12

So for each bit the cap goes up by a factor 4. If you half the Vdd you need also 4 times the cap size. These should be charged from the supply. The energy needed from the supply is then double than that with the orginal voltage.

So voltage scaling leads to less effcient ADC's. Or someone say analog scaling is death. True, digital could improve and support ADC functions but not noise!