Leakage current measurement of this STOP circuit

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meeyaw

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Hi all,

I am currently studying current measurements of circuits when I suddenly got stalled by this block that I am currently studying. Diagrams below are provided below:

Block:


Behavior:


The block intends to be a STOP_CLOCK cell. By the name itself, it will stop CLK_IN whenever STOP goes low, while passing to the output when STOP is high, as you can see in the second image. STOP_EN enables the main STOP cell.

With this type of circuit, how can I measure the leakage current of the whole block? Is it during the STOP is low or the STOP is high?

Thanks,
meeyaw
 

The term "leakage current" should be used in a static (idle) state of the circuit, otherwise in a dynamic context would depend on the behavior and speed of the signals applied. Anyway, as far as I can see, a bare bloc diagram do no suffice, but the technology/topology which with the circuit was assembled/syntesized, the environment conditions ( supply voltage, temperature ). A stand alone simulation could be done with some spice-like simulator, just computing the average current, I guess.
 
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    meeyaw

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meeyaw said:
... how can I measure the leakage current of the whole block? Is it during the STOP is low or the STOP is high?
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In any case I'd measure with STOP_EN low, because this is the static or idle state mentioned by André (above). There are still 4 possible combinations for CLK_IN and STOP. For worst case I'd check all 4 of them. Without knowing the internal circuit you can't decide which of them provides the largest leakage current.
 
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