ldpc decoder implementation-reg

[arunshanmugam46]

hi,
i am implementing ldpc decoder using minsum algo in verilog..my doubt is how to use real variables (eg:3.3456) in verilog without using the keyword real..

 

[elockpicker]

Hi,
'Real' type in Verilog is not synthesizable.
If you really need to handle 'real' values then it is possible to use the IP-Cores that provide functions on 'real' values, for example addition,multiplication, square root,... There are many free IP-Cores for that matter...

The other option is using fixed-point numbers. Verilog can inherently handle fixed-points but it requires a little experience.

using 'real' numbers can add extra overhead in area and time to you project.
Choosing fixed-points, on the other hand, has its own limitations.