Hardware implementation of long FIR filter

[himadri_debnath]

I have designed a multistage FIR filter for my project. Each of these filter has long number of taps. I want to implement it in Verilog but I am finding it difficult to write such a long verilog code. Is there any other shortcut method? I have tried MATLAB hdl coder but it is giving complex results which I didn't like. I am using xilinx Vivado.

 

[barry]

Since each stage is a multiply/accumulate cant you just use something like the VHDL generste construct?

 

[danadakk]

How many taps in filter ? You cascading multiple FIR filters or just
the one ? Sampling rate ?


Regards, Dana.

 

[himadri_debnath]

How many taps in filter ? You cascading multiple FIR filters or just
the one ? Sampling rate ?


Regards, Dana.

I have 4 filters. 1st one has 242 taps, 2nd - 97 taps, 3rd and 4th 26 taps each. Total 391 taps. I am actually doing sample rate conversion. Converting it from 44.1 kHz to 48kHz.

 

[FvM]

For low sample rate, a RAM based sequential implementation would be preferred for resource economy.

I don't know which FIR tools are provided by Xilinx, I'm fully satisfied with Altera/Intel FIR compiler.

 

[student_078]

Since your data rate is only in the kilohertz range, why not use serial approach with a MHz clock?
You can store sample and coefficients in block RAM.