Maitry07
Full Member level 3

Hello support team,
I have one fixed gain LNA at the input of the RF direct sampling receiver. This LNA is to increase the dynamic range of the RF-ADC inside the Direct sampling receiver. As the output of direct sampling receiver is in the form of I and Q samples which use DDCalgorithm.
At the DDC output, I need to implement Digital gain compensation technique for the fixed gain LNA to have actual amplitude. can you please suggest a suitable technique for the implementation of digital gain compensation technique in FPGA for the external fixed gain LNA?
I have one fixed gain LNA at the input of the RF direct sampling receiver. This LNA is to increase the dynamic range of the RF-ADC inside the Direct sampling receiver. As the output of direct sampling receiver is in the form of I and Q samples which use DDCalgorithm.
At the DDC output, I need to implement Digital gain compensation technique for the fixed gain LNA to have actual amplitude. can you please suggest a suitable technique for the implementation of digital gain compensation technique in FPGA for the external fixed gain LNA?