tomereli
Newbie level 1
Hi,
I am a student and very new to HDL, i have an assignment - writing verilog code for the ST7066U LCD on my board.
I am trying to write a basic FSM which will interface the ST7066U chip.
I have a working example which uses only one always block ( always (posedge clk) ) but from what i've learned so far online and from books, this is a wrong approach and the right one should be using 2 always blocks - one for the combinational part and one for the sequencial part like that:
always (posedge clk, negedge reset)//sequencial part
if(~reset)
....
else
currentState <= nextState;
always (*) //combinational part
case(currentState)
case boot: ...
//delay 40ms is needed here
case init:
...//here i need to plant the initilization routine
...
...
The thing i can't seem to get is how to implement the delays... using the 2 always blocks approach i can easilly decide on the states and outputs, but i don't know how to insert the delays..
Thanks in advance for any help...
I am a student and very new to HDL, i have an assignment - writing verilog code for the ST7066U LCD on my board.
I am trying to write a basic FSM which will interface the ST7066U chip.
I have a working example which uses only one always block ( always (posedge clk) ) but from what i've learned so far online and from books, this is a wrong approach and the right one should be using 2 always blocks - one for the combinational part and one for the sequencial part like that:
always (posedge clk, negedge reset)//sequencial part
if(~reset)
....
else
currentState <= nextState;
always (*) //combinational part
case(currentState)
case boot: ...
//delay 40ms is needed here
case init:
...//here i need to plant the initilization routine
...
...
The thing i can't seem to get is how to implement the delays... using the 2 always blocks approach i can easilly decide on the states and outputs, but i don't know how to insert the delays..
Thanks in advance for any help...