LCD controller FSM Spartan-3A/3AN FPGA Starter Kit

[tomereli]

Hi,
I am a student and very new to HDL, i have an assignment - writing verilog code for the ST7066U LCD on my board.
I am trying to write a basic FSM which will interface the ST7066U chip.
I have a working example which uses only one always block ( always (posedge clk) ) but from what i've learned so far online and from books, this is a wrong approach and the right one should be using 2 always blocks - one for the combinational part and one for the sequencial part like that:

always (posedge clk, negedge reset)//sequencial part
if(~reset)
....
else
currentState <= nextState;


always (*) //combinational part
case(currentState)
case boot: ...
//delay 40ms is needed here
case init:
...//here i need to plant the initilization routine
...
...


The thing i can't seem to get is how to implement the delays... using the 2 always blocks approach i can easilly decide on the states and outputs, but i don't know how to insert the delays..

Thanks in advance for any help...

 

[pmat]

Hi,
you have to de-associate the FSM itself from the delays between the state transitions.

Calculate the number of clock cycles which correspond to 40ms. Start the counter which
counts this number of cycles at the boot state. Whenever the counter reaches the number
of cycles you are interested in, generate a signal, i.e. counted40ms.
Then use this signal in the FSM combinational part and if you are at the boot state and the
counted40ms signal is raised then go to init state.
Try to keep your FSMs clean and dont push unrelated code into FSM's blocks.

Pavlos

 

[ravics]

I think this would work with slight modifications.

 

[joaoprata]

What u mean with slight modifications?
This project wont run like he is?
thks