Yeah, Its Length .It was by mistake.
Ok. That means you are calculating the area with respect to Gate length, Width and Length of MOS .
What about the routing, connections from pMOS to nmOS??.
technology means gate length.
Alos remember that there is NWELL for pMOS which consumes area. So, finally when you determine the poly routing, metal routing, the NWELL area -> the area will be same as given.
You cannot calculate area of layout by its length and width, routing is important part of layut.