Layout size question in standand cell.

[john7796]

Dear All,

The standand cell information is following:
.subckt BUFX1 Y A
X_g0 Y net7 inv pl=0.18u pw=1.92u nl=0.18u nw=1.3u
X_g1 net7 A inv pl=0.18u pw=0.71u nl=0.18u nw=0.47u
.ends BUFX1

The cell size is 0.18*(1.92+1.3+0.71+0.47)=0.18um*4.4um

But the data sheet shows the standand cell size is 5um*2.6um.

What happened to the size information?

John

 

[Prashanthanilm]

Are you calculating the area?

Can you please tell how did you calculate those values.

I mean the cell size = 0.18* (? How come)

 

[john7796]

Dear Prashanthanilm,

1. Yes, the value is for area.
2. 0.18um comes from pl=nl=0.18um. This is for 0.18um process.

John

 

[Prashanthanilm]

I was talking about (1.92+1.3+0.71+0.47) value.

0.18um means the poly width right? How does it helps in area calculation.

 

[john7796]

Dear Prashanthanilm,

pl=0.18u pw=1.92u nl=0.18u nw=1.3u => Transistor ratio W/L => pl and nl => L ; pw and nw = W.

0.18um means transistor gate length for 0.18um process.


John

 

[Prashanthanilm]

Yeah, Its Length .It was by mistake.

Ok. That means you are calculating the area with respect to Gate length, Width and Length of MOS .

What about the routing, connections from pMOS to nmOS??.

technology means gate length.

Alos remember that there is NWELL for pMOS which consumes area. So, finally when you determine the poly routing, metal routing, the NWELL area -> the area will be same as given.

You cannot calculate area of layout by its length and width, routing is important part of layut.

 

[john7796]

Dear Prashanthanilm,

What factor will affect the NWELL area ?

John

 

[Prashanthanilm]

Its DRC rules. The fab unit will have constraint that the NWELL is some distance far from active region. The distance varies with respect to Technology.

DRC->Design Rule Check.

All the layers used in Layout will have DRC rule check to check that the layers won't overlap unexpectedly in the time of Masking.