LAYOUT : MOS connected to IO PADs

[ssuchitav]

Hi,

I have some NMOS transistors with DRAIN connected to IO pads. As per ESD guide lines m putting RPO layer on the DRAINS to avoid current crowding, but it gives problem in the extraction of the other devices which are stacked with the same NMOS. Any clue here?

thanks in advance.

 

[sat]

A picture would help.

Hope in the extraction rules, ESDDUMMY and other device DUMMY layers been properly taken into account. The reason is inside ESD, device recognitions might have slightly different layer combination than non-ESD ones.