Layout-dependent effect: tsmc 40nm CMOS problem

[shockingshockley]

I am currently doing a current mirror circuit using 40nm process. The reference current is okay in pre-layout simulation but becomes lower during post-layout simulation. Is the placement of the devices affect the resulting current? COuld you give me some layout techniques to counter these layout-dependent effects. Thanks in advance.

 

[Dominik Przyborowski]

Is the placement of the devices affect the resulting current?

Yes.
Look for well proximity effects (WPE) and length of diffusion (LOD). WPE is reflected in sca, scb and scc parameters while LOD might be reflected in lle_*.

 

[Ans5671]

1. You have to keep the devices as close as possible for good matching. You could try the Common Centroid layout.
2. If you are using fingers then look for threshold voltage variations. Check various parameters in schematic vs layout results.

 

[martinnl]

With a question like this an image is good to include if you want specific pointers.

But I agree with Dominik, most probably wpe and/or lod. The LOD effect is seen in parameters sa, sb, and sc if I'm not mistaken. Check the spectre/spice netlist and compare the instances.

I know tsmc 40nm has decent documentation of these effects and gives examples, take a look in the PDK docs.

 

[timof]

Two possible root causes:

1. Device systematic mismatch, because of layout-dependent effects (discussed in this thread earlier).
2. Parasitic effects - IR drop, metal debiasing, IR drop mismatch, etc.