Latch Up basics in CMOS inveter

[joely2k]

cmos inverter and latchup

Harlow, can anyone of you briefly explain

what is latch up,

How can a normal CMOS inverter (poly, diffusions, substrate, nwells, metals) create the latch up?

What is the effect to the circuit/performance and current?

And how ntaps, ptaps can solve this problem?

I read alot of the things but cant really understand, can someone explain me in terms of the electrons, holes and depletion zones, channels.. so I can easily understand it Thanks

 

[Syukri]

definition of latch up

firstly remember this, latch up is happening in CMOS technology....ok

then remeber back that transistor in buld by using n type and p type, mostly in BJT circuit..

If u had a CMOS circuit cross section take it now..inverter will be the best to study..

The p-substarete is p type, then we got n diffusion and p diffusion futhermore to put p diffusion we need the nwell

p substrate is dop with n well then dop with p type...resulting pnp transistor(BJT)

n diffusion from another transistor is dop on p substrate and got connection of n well from the transistor before...resulting npn transistor(BJT)..

These two transistor making a loop than when the current is supplied to them, transistor is on

If the loop gain is greater than 1 ( Berkausen Criterion ), then is will continue increse and drawing a large current from Vdd...means your CMOS circuit is not functioning

THIS IS CALLED LATCH UP EFFECT....Ok

Sorry I can explain it your way, because it's difficult to explain it that way..anayway I'm a designer so my solid state is not that good....

Ptabs and ntabs is concernign on the doping level, proper doping level will lead to gain less than 1 and preveting the current to increase

Good Luck

 

[wwfeda]

npn transistor latch

Assuming you have a picture of the parasitic bjts as a reference which can be found in most cmos text book explaning latchup.

Latch up is basically a positive feedback circuit made up of the paracitic npn and pnp inside your cmos. Remember that to turn on a npn or a pnp, you just need to have that Vbe voltage. There are resistances in your mosfet bulk, drain, source. If the current is big enough and the resistance in the bulk is high enough, it will create that a voltage drop (vbe) and it will start to turn on one of the transistor. This transistor will start to draw current, in which that current will start to turn on the other transistor. Now, since this transistor is turning on, it will in return turn on the original transistor. So, you see a positive feedback going on, and when both transistors are fully on, you have a latch up.

There are a few ways to prevent latch up from happening. One of the easiest way is to dope the bulk layer higher, so that the inert resistivity is low. It will need to have a much higher current to create that initial voltage drop (vbe). If the initial transistor doesn't turn on, then you won't have a latch up.

Of course, doping bulk at a higher lvl means you have a much higher Vt. There is always some tradeoff somewhere.

 

[blackspeed]

src latchup

There are a few ways to prevent latch up from happening. One of the easiest way is to dope the bulk layer higher, so that the inert resistivity is low. It will need to have a much higher current to create that initial voltage drop (vbe). If the initial transistor doesn't turn on, then you won't have a latch up.

Of course, doping bulk at a higher lvl means you have a much higher Vt. There is always some tradeoff somewhere.

I don't think that a stable process will meet your requirement of doping bulk at a higher lvl for you want to avoid latch up.
The best way is enlarge the space of P diffusion in NW to n diffusion in P sub, and also the tie down and tie up to seperate the PMOS & NMOS is better!

 

[electronics_kumar]

cmos latch positive feedback

By using Guard rings we can avoid Latchup problem

 

[YESH_23]

ic design cmos avoid latchup

actually one ore definition of latch up is to create a low ipedence path between VDD and GND.

there are few ways to reduce this effect but we cannot complettely eliminate this.

one way is ti see to that the voltage drop the base resistors in the paracitic transistors formed should not be equal to the forward bais voltage of the transistors.for that the base resistors are the n and p well resistance.so that these should be less that they dont crete voltage drop.

another way is that we can determine the voltage swing in which the latch up occurs and shoild take care that the vdd and gnd potential never reaches that swing.

common way is to place gaurd ring where ever place is there.

 

[vbhupendra]

cmos latchup

Creation of low impedance path b/w the power supply rails by the triggering of parasitic SCRs. It can be triggered if source of NMOS pulled below gnd or source of PMOS pulled above VDD and
Beta X Beta(p) > 1

Prevention :- reduce beta of parasitic transistors. Achieved by increasing spacing which in turn increases width of neutral base regions of parasitic transistors. Another way is to increase the dopant concentration of sub and well. Both of these reduces beta of transistors. Or provide alternate collector to remove unwanted minority carriers i.e. guard rings. Guard Rings consist of metal layer connections which are connected to sub taps. Couples noise to gnd.

· Use guard rings.
· Reduce well and sub res by using sub and well contacts as close as possible to the src connections.
· Layout n & p channel transistors such that all nmos placed close to gnd and pmos to VDD.
· Maintain sufficient spacing b/w N & P MOS.

 

[p.sivakumar]

latch up problem in cmos

Hi

This is sivakuamr GDA Technologies ltd as analog designer.According to my knowledge,Latchup is sevier effect in standard cell layouts ,it is the efffect which is due to the two parasitic transistors formed internally in the standard cell by the
p-n-p & n-p-n layers.thes two transistors are called as pnp,npn perasitic transistors.
Due to this effect the cell will draws extra current and some times the whole cell will damage .So,to avoid this effect we have to insert gaurd rings in layout.for forther information go through neel weste book(cmos vlsi design).

 

[Prashanthanilm]

Re: cmos latch positive feedback

By using Guard rings we can avoid Latchup problem

how?? please explain in detail?

 

[dick_freebird]

You know, there are lots of decent presentations on this
subject out there for the Googling. Pictures, and everything.