tromeros
Member level 1
Hi,
I have designed a spiral inductor in Cadence Virtuoso and in the Schematics I designed the equivalent pi-circuit with lumped passive elements. I want to make LVS. The layout passes successfully the DRC check. However in after the LVS running I get the message that there is a short between the ports, which makes sense since the ports are on the edges of the inductor.
My question is what should I do to pass succesfully the LVS?
Thanx in advance!
I have designed a spiral inductor in Cadence Virtuoso and in the Schematics I designed the equivalent pi-circuit with lumped passive elements. I want to make LVS. The layout passes successfully the DRC check. However in after the LVS running I get the message that there is a short between the ports, which makes sense since the ports are on the edges of the inductor.
My question is what should I do to pass succesfully the LVS?
Thanx in advance!