Re: more abt synthesis & blackboxing
thanks!
does that mean that i dont need to give any timing constraints at the top level. ..
i did vot u had written. and i got no timing violations reported, whereas, a no. of the submodules had timing violations at the time of synthesis.. i was just wondering , shouldn the timing violations appear at the top level as well??
also,
how do i black box a sub module so that its design is not read etc, so that the tool doesn issue warnings( cos i have a submod whose design i do not have). is making a dummy module (with only interface) equivalent to creating a black box (not exactly bu t in essence??)??
thanks again!