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Joining synthesized sub-mods at the top level

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cosmonutt

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hi!

could anyone send me an example synthesis script for a bottom-up synthesis. at the top level i just need to join in the already synthesized sub-mods.
vot all do i need to specify at the top level??

thanks!!
 

anssprasad

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Re: more abt synthesis

cosmonutt said:
hi!

could anyone send me an example synthesis script for a bottom-up synthesis. at the top level i just need to join in the already synthesized sub-mods.
vot all do i need to specify at the top level??

thanks!!

Hi
Just read in the top file with the submods instantiated in it and the rest of the flow would be common to all flows. One thing to take care of is set the current design after reading your files in any order.

read_verilog <filename> <filename> <filename> <filename>
set current_design <top module name>
link
check_design
check_timing
compile
.........
 

    cosmonutt

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cosmonutt

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Re: more abt synthesis & blackboxing

thanks!

does that mean that i dont need to give any timing constraints at the top level. ..
i did vot u had written. and i got no timing violations reported, whereas, a no. of the submodules had timing violations at the time of synthesis.. i was just wondering , shouldn the timing violations appear at the top level as well??


also,

how do i black box a sub module so that its design is not read etc, so that the tool doesn issue warnings( cos i have a submod whose design i do not have). is making a dummy module (with only interface) equivalent to creating a black box (not exactly bu t in essence??)??

thanks again!
 

anssprasad

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Re: more abt synthesis & blackboxing

Hi
No, you should give timing constraints at the top level. Using a dummy module is a good idea to black box a module.

Thanks
Prasad.
 

cosmonutt

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Re: more abt synthesis

but i did give timing constraints at the top level! and still got no violations.. thats why im not sure if my designs were linked properly..

also, it would help if u could me vot is the usual way to black box a module..
 

anssprasad

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Re: more abt synthesis

I did not find any other commands specially used for black boxing a module like the commands you find in LEC. I have also come across people using a dummy interface only when they do not have the RTL or a model for a particular module
 

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Re: more abt synthesis

oh ok. thanks!

another question that has been unanswered for quite a while now is
do u know vot this warning means??
module "xyz" was not elaborated because it has the template attribute. it was saved as a template instead.
??
 

anssprasad

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Re: more abt synthesis

The warning could be because that module is a library macro or a model and not RTL actually which cannot be elaborated.

I cannot tell you for sure though!!
 

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Re: more abt synthesis

okk. thanks tons!
 

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