Is it possible, that you did not streamout all levels of hierarchy? I remember, that the command in ICC have such options. Check the man for this command.
Incorrect. The Milkyway database (that IC compiler uses) may contain all needed info about layout of the cells (in different views FRAM, CEL). So, it is possible that not all hierarchy levels were written into GDS. Option is child_depth.
In Innovus you can write any label you want and associate any datatype to it. Maybe ICC has something similar but I wouldn't know, ICC is not something I use regularly. Maybe look for a create_label command or create_text, something like that.I just have one issue left. When I import the GDSII file (generated by IC Compiler) into Custom Compiler and run LVS, I see that pin labels are not preserved.
Dear sir, I've met the problem that cells can not be shown in virtuoso and I've tried some suggestions under this thread but it didn't work out. Since you have solved it, would you mind giving some more specific instructions about importing ICC gds and showing all cells in virtuoso, I'm really curious about what files I really need to make this work and ways to deal with them.Thank you @ThisIsNotSam and @oratie. Eventually, I found a way to resolve the issues mentioned above. Now, I'm struggling with the issue in the case of simulating the schematic. After I imported the schematic using veriliog import-in, I have a symbol view and schematic view of the circuit( inv). I'll add pictures here to explain the hierarchy and then I'll state the problem I'm facing.
View attachment 165063
Fig. 1: Hierarchy 1 (symbol)
View attachment 165060
Fig. 2: Hierarchy 2 (schematic -- generated after I imported from ICC)
View attachment 165061
Fig. 3: Hierarchy 3 (Standard cell to which schematic and symbol is bounded)
Here, I created a new cell and connected voltages and gnd as shown in Fig. 1. You can descend on that symbol to check the other hierarchies as shown in Fig. 2 and Fig. 3 respectively. Now, when I try to do the simulation, the HSPICE simulation runs without errors but I get the following warnings:
Checking "my_lib_32/inv/schematic"
[warning] Floating I/O Pins
I/O pin 'VDD' is floating
I/O pin 'VSS' is floating
0 Error(s),2 Warning(s),0 Message(s) found in "my_lib_32/inv/schematic"
Which is also visible from Fig. 2. So, eventually, I get an incorrect output though there are no errors or warnings from the top-level ( the warning generates from the second level).
I tried to do drc, lvs and pex. Everything worked correctly using the same schematic. only when I'm trying to simulate, it is showing this warning.
I'm also attaching the netlist the simulator is generating, it seems okay to me.
*Custom Compiler Version M-2017.03-SP1-1
*Thu Oct 22 15:45:23 2020
.GLOBAL gnd!
********************************************************************************
* Library : saed32nm_stdcell_hvt_oa
* Cell : INVX1_HVT
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt invx1_hvt a y
xp y a vdd vdd p105_hvt w=0.8u l=0.03u nf=1.0 m=1
xn y a vss vss n105_hvt w=0.42u l=0.03u nf=1.0 m=1
.ends invx1_hvt
********************************************************************************
* Library : my_lib_32
* Cell : inv
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt inv o1 i1 vdd vss
xu2 i1 o1 invx1_hvt
.ends inv
********************************************************************************
* Library : my_lib_32
* Cell : inv_test_2
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
r16 o1 gnd! r=1G
xi3 o1 i1 vdd gnd! inv
v12 vdd gnd! dc=1
v8 i1 gnd! dc=0 pulse ( 0 1 0 5p 5p 5n 10n )
In this circumstance, do you guys have any suggestions for me? I would really appreciate your help.
Thanks
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