issues about synopsys dft compiler

[JesseKing]

design compiler integreted with DFT complier can synthesis rtl code to a scan chain ready netlist, but I dont know how to generate those test control signals and components.

For example,
How to connect port enable the "shift" cycle named scan_en to all dffs?
When memories are used in design, a bypass mux controlled by signal scan_mode should be added; when tri-state gates are used in design, decoders and mux should be add to drive the tri-state gates' enable pins; when gated clocks or set/reset signals exist in design, mux should be added too. How are these components introduced? Are they generated automatically by dft compiler or manully introduced in rtl code?

Best regards,
Jesse

 

[wkong_zhu]

I add scan_mode manually, and set it to 1 when insert DFT. synopsys has some commands to set the scan_en, scan_clk, DI, DO, You can find it in SOLD manual.
You'd better fix inout to one direction, and bypass sram by yourself instead of DC tools, even though it can do.

 

[akrlot]

to create ports you can introduce these commands into your synthesis script:
create_port -direction "in" {test_se}
set_scan_signal test_scan_enable -port test_se
use similiar commands to create test_so and test_si
i think the violations you talked about are fixed automatically and the generated netlist contains a synthesized scan chain with fixation of dft rules violations(gated clock...) so you don't need to edit your rtl code.

 

[peen1]

hello akrlot,
Why do you need test_so and test_si? I thought that you can use the normal input output ports of the design to feed/retrive the test vectors?

thanks

 

[akrlot]

hello akrlot,
Why do you need test_so and test_si? I thought that you can use the normal input output ports of the design to feed/retrive the test vectors?

thanks

you are right if you want to reduce the number of ports you can use existing ones to feed test vectors

 

[JesseKing]

I add scan_mode manually, and set it to 1 when insert DFT. synopsys has some commands to set the scan_en, scan_clk, DI, DO, You can find it in SOLD manual.
You'd better fix inout to one direction, and bypass sram by yourself instead of DC tools, even though it can do.

hello, wkong_zhu.
and i still want to know whether DFT compiler built in dc can automatically to generate these ports/pins, or just set ports/pins that already exit to be scan related pins.

 

[akrlot]

I add scan_mode manually, and set it to 1 when insert DFT. synopsys has some commands to set the scan_en, scan_clk, DI, DO, You can find it in SOLD manual.
You'd better fix inout to one direction, and bypass sram by yourself instead of DC tools, even though it can do.

hello, wkong_zhu.
and i still want to know whether DFT compiler built in dc can automatically to generate these ports/pins, or just set ports/pins that already exit to be scan related pins.

DFT compiler creates automatically these ports (test_si,test_so,test_se). So you can let it create them automatically or use the commands i gave to you to create these ports manually or choose them among functional ports (if you want to minimize the number of pins)