Issue with Estimating asic gate count using DC

[onkars]

Hi,

I am trying to estimate the gate count of my design. I do not have a target technology library at hand.

Hence I decided to synthesize the design using Synopsys Design Compiler and get the netlist in GTECH.
I assume that GTECH_NAND2 is equal to 1 cell. Then i plan to estimate the cell count of the design (in terms of NAND2 cells) by using relations such as: 1 flip-flop = 6 cells, 1 inverter = 0.5 cell, AND2 = 1.5 cells etc.

BUT the problem I am facing is that the gtech netlist given by DC contains components like SELECT_OP_2.1_2.1_1, MUX_OP_2_1_2, SELECT_OP_2.8_2.1_8 and many more.
How can I estimate the cell counts for these -- and that too because they have so many variations?
Is there a way to prevent the Presto HDL compiler from using these components and only use GTECH_AND and ORs?

Kindly advise.

Thank you.

 

[jkarthikr]

Hi Onkars ,

I am just curious to know the significance of finding gate count, without a technology
library at hand . Even if you want to compare two different architectures for relative area, you could do it with some technology library

In this case, maybe you can specify those cells as 'dont use'. If there are too many variants,
maybe wilcard characters can be used ?

 

[onkars]

Thank Karthik.

Actually I do not have any technology lib with me to use -- hence the approach.

 

[asicganesh]

You can download the technology library from the fab websites.. try tsmc 65nm library