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A flip flop cannot be triggered at both the positive edge and negative edgeBetter you start with your opinion, why do you think this code is might not synthesize?
I know it will not be syth for FPGAs, as FPGAs do not have flip-flops that can trigger on both edges of a clock.
But for ASICs I think design syth. could be possible. e.g. - We know that DDR memories work on both clock-edges.
always @ (posedge clk, negedge clk)
always @ (edge clk)
It's not synthesizable standalone in a module unless it's inside a procedural statement, i.e. always or initial.It's of course synthesizable. If you don't specify OUT to be initialized to 0 (e.g. by initial block or general synthesis constraints), the statement might be synthesized as constant 1.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 module test ( output reg q, input d, input clk ); @(posedge clk); // this line reports an error on the @ q = d; endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 // using initial statement: module test1 ( output reg q, input d, input clk ); initial begin forever begin @(posedge clk); q = d; end end endmodule // using always statement: module test2 ( output reg q, input d, input clk ); always @* begin @(posedge clk); q = d; end endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 module test2 ( output reg q, input d, input clk ); always @(posedge clk) begin q <= d; end // optionally the one liner: // always @(posedge clk) q <= d; endmodule
I mean if this is synthesizableCode:always @ (posedge clk1) begin @ (posedge clk2) OUT=1; end