is this a pipeline design ?

[sevid]

hi, everyone

if my design consists of 3 modules, of course, their I/Os have relationships.

certainly, my top design connects them together.

then, from the system structure point of view, can i call this design (or the top module/design) a pipeline if only the outputs of each module are latched ??

if not, how to design a pipeline system with verilogHDL? and if it has four levels such as IF,ID,EXE, and WB.

pls give ur view and we'll very appreciate.

sevid

 

[eeeraghu]

not exactly, if outputs of each module are registered it may not be pipeline.
if in a particular path a point is registered and the handshake and control of that point must also act exactly & affect accordingly. Moreover pipelined architecture is what that current input does not affect the current output. hope i explained rightly.