Is this a good way to get double-edge clocking in CPLD

[supercat]

In a CPLD which supports async preset/reset of flip flops, and allows each latch to be configured for either rising edge or falling-edge trigger, but not both, would the following be a good approach to simulating a double-edge-trigger latch:

latch1.clk = Clock;
latch2.clk = !Clock;
latch1.d = Data;
latch2.d = Data;
latch1.ap = !Clock & latch2.q & !latch1.q;
latch1.ar = !Clock & !latch2.q & latch1.q;
latch2.ap = Clock & latch1.q & !latch2.q;
latch2.ar = Clock & !latch1.1 & latch2.q;

At least in theory, if the clock is stable, latch1 and latch2 will be made to match. When the clock changes state, latch1 or latch2 will grab the data, and then the other latch will conform to it.

The latch-to-output propagation delay will be different for rising and falling edges (which is faster will depend upon whether one uses latch1 or latch2) but I would expect that things should switch cleanly unless a setup/hold violation between clock and data causes a latch to go metastable. Unless the clock has runt pulses or is otherwise too fast, I wouldn't think metastability would be any worse than with a normal latch.

Has anyone tried such an approach before? Are there any gotchas?

 

[manosan]

But I guess in effect you have two latches... one working at pos-edge and other at neg-edge...

 

[supercat]

But I guess in effect you have two latches... one working at pos-edge and other at neg-edge...

It is two FF's, but both FF's should end up changing on each clock edge. For example, suppose both FF's and the clock were low, and a rising clock edge arrived.

Until the clock arrived, none of the async preset/reset terms would be active since they all require, as part of their condition, that the two FF's differ. The rising edge clock would load the data into the first FF.

At that point, the clock would be high, the first FF would be high, and the second FF would be low. That is the combination of conditions necessary for the second FF's asynchronous preset. This would switch the second FF to high, matching the first one. Once the output switched, the second FF's preset async-preset output would go away, but by then the FF should be fully switched.

The net effect should be that on a rising clock edge, the first FF would grab the state of the data line directly and then propagate it to the second; on a falling clock edge, the second FF should grab it directly and propagate it to the first. If the rest of one's circuitry only used the output from the first latch, the propagation time would be different for rising and falling clock edges, but the sample and hold requirements should be essentially the same for both edges.

Provided the clock is slow enough that things can settle between clock edges, the only race conditions I can see would be:

-1- Turning off the reset/preset signals when a FF switches; I think it is probably reasonable to figure that by the time the effect of a reset/preset can propagate around through the CPLD feedback path, the FF's own internal feedback is satisfied with the length of the reset/preset pulse.

-2- Really slow clock reaching logic versus clocking the register; if latch1 were clocked by a rising edge, but the rest of the logic continued to see clock as low, the high output from latch1 and low output of latch2 could cause latch1's reset signal to become active, erroneously. clearing latch1. In practice, it seems unlikely that the effect of the clock signal could propagate out of latch1 while he other logic still saw latch1 as low.

Are there any other gotchas?