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Is the peak di/dt of 500MA/s acceptable in simulation phase?

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chang830

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The peak di/dt issue

Hi,
For my TTL/CMOS buffer design, i found the peak di/dt is high up to ~500MA/s in simulation. I know,it will cause the serious vdd/gnd bounce.But we know, in actual conditions, it is not so pessimistic.Many solutions will be used to improve it, e.g, the bypass cap in PCB bord.

I want to know, is 500MA/s current change rate be tolerable in simulation phase?
Will it cause any EMI concern?

Can anyone shed some light on it?

Thanks
 

Re: The peak di/dt issue

I think 500ma/s is not a big value,

perhaps you've given a wrong value.

best regards


chang830 said:
Hi,
For my TTL/CMOS buffer design, i found the peak di/dt is high up to ~500MA/s in simulation. I know,it will cause the serious vdd/gnd bounce.But we know, in actual conditions, it is not so pessimistic.Many solutions will be used to improve it, e.g, the bypass cap in PCB bord.

I want to know, is 500MA/s current change rate be tolerable in simulation phase?
Will it cause any EMI concern?

Can anyone shed some light on it?

Thanks
 

Re: The peak di/dt issue

funster said:
I think 500ma/s is not a big value,

perhaps you've given a wrong value.

best regards


chang830 said:
Hi,
For my TTL/CMOS buffer design, i found the peak di/dt is high up to ~500MA/s in simulation. I know,it will cause the serious vdd/gnd bounce.But we know, in actual conditions, it is not so pessimistic.Many solutions will be used to improve it, e.g, the bypass cap in PCB bord.

I want to know, is 500MA/s current change rate be tolerable in simulation phase?
Will it cause any EMI concern?

Can anyone shed some light on it?

Thanks

It is MA/s not mA/s, it is not a big value? 1M is mega.
 

Re: The peak di/dt issue

not a big issue.
 

The peak di/dt issue

Use simple formula Usso_noise=L*(di/dt). For standart packages L~2..20 nH. Assume L=5nH than Vsso_noise=2,5V. I think in your circuit noise margin is less. Use output slew rate control technique and decrease crossbar currents (for example use break-before-make circuit for non-agressive design) if necessary. U can decrease L when use more pins.
 

    chang830

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