chang830
Full Member level 5
The peak di/dt issue
Hi,
For my TTL/CMOS buffer design, i found the peak di/dt is high up to ~500MA/s in simulation. I know,it will cause the serious vdd/gnd bounce.But we know, in actual conditions, it is not so pessimistic.Many solutions will be used to improve it, e.g, the bypass cap in PCB bord.
I want to know, is 500MA/s current change rate be tolerable in simulation phase?
Will it cause any EMI concern?
Can anyone shed some light on it?
Thanks
Hi,
For my TTL/CMOS buffer design, i found the peak di/dt is high up to ~500MA/s in simulation. I know,it will cause the serious vdd/gnd bounce.But we know, in actual conditions, it is not so pessimistic.Many solutions will be used to improve it, e.g, the bypass cap in PCB bord.
I want to know, is 500MA/s current change rate be tolerable in simulation phase?
Will it cause any EMI concern?
Can anyone shed some light on it?
Thanks