When designing an IC layout, does the width of the metal need to ensure peak current?

[goatmxj666]

Hello.

I am doing an IC layout in 180nm CMOS process.

I have connected a chain of inverters to drive the CLK signal of 12 D-FF.

The total combined size of the mosfets which the CLK signals of the D-FFs are connected is approximately pmos=24um, nmos=24um gates.

At this time, I connected the inverter chain to the CLK in the order of 2um, 4um, 8um, 16um (NMOS is half of this) based on PMOS.

However, the peak current flowing is about 3mA.

The metal I am using is 1mA/1um.

So I need to layout the metal at 3um, but when I draw it, it is quite thick.

So i was wondering if i should route the metal in 3um like i do now or is there any other better way.

Any answer would be really helpful to me.

Thanks.

 

[dick_freebird]

I use a 10x limit for reversing, balanced current (AC) and for an upper bound to peak unidirectional current, subject also to the average being below DC Jmax.

 

[sidun.av]

I think you should refer to the Design Rules Manual (DRM) for your process. Usually they do provide a corresponding formula to recalculate AC current density to DC. As dick_freebird mentioned, usually, AC current reqiures about 10 times less width rather than DC current, but this assumption will be valid only for a certain current peak duration (relative to the period) which you should check with DRM.

 

[dick_freebird]

This also has underlying process construction
details to consider (must derive from physics of
failure).

For example an all-aluminum (planes and vias)
system will let electromigration proceed through
layer, via, layer and the material drift somewhat
maintains the distribution (choke-points where
J is most elevated, aside - uniform J is constant /
uniform-ish material drift).

But tungsten plugs are hard migration barriers so
what you see there is, material accumulates at the
"upstream" side and "wanders away" from the
downstream of current flow. You can see worse
EM outcomes from equal interconnect-plane
material properties, using W plug vias.

Not to mention that the plugs are nasty little heaters
that locally raise interconnect temp (the prime
accelerant) and can torpedo your current capacity
(rules, not facts) if analysis fails to comprehend /
account for / put to lifetime model at stress-temp
and stress-self-heating.

Of course by the time a designer sees the rules, all
of this has long since been "blessed" and any effort
to check work will meet resistance (heh). Believe me,
I have gone down that road (finding and fixing bad
electromigration test conduct and analysis and the
clowns who made it so) more than once.

 

[sidun.av]

This also has underlying process construction
details to consider (must derive from physics of
failure).

For example an all-aluminum (planes and vias)
system will let electromigration proceed through
layer, via, layer and the material drift somewhat
maintains the distribution (choke-points where
J is most elevated, aside - uniform J is constant /
uniform-ish material drift).

But tungsten plugs are hard migration barriers so
what you see there is, material accumulates at the
"upstream" side and "wanders away" from the
downstream of current flow. You can see worse
EM outcomes from equal interconnect-plane
material properties, using W plug vias.

Not to mention that the plugs are nasty little heaters
that locally raise interconnect temp (the prime
accelerant) and can torpedo your current capacity
(rules, not facts) if analysis fails to comprehend /
account for / put to lifetime model at stress-temp
and stress-self-heating.

Of course by the time a designer sees the rules, all
of this has long since been "blessed" and any effort
to check work will meet resistance (heh). Believe me,
I have gone down that road (finding and fixing bad
electromigration test conduct and analysis and the
clowns who made it so) more than once.

That's a very interesting observation, thank you for sharing your experience!

 

[goatmxj666]

This also has underlying process construction
details to consider (must derive from physics of
failure).

For example an all-aluminum (planes and vias)
system will let electromigration proceed through
layer, via, layer and the material drift somewhat
maintains the distribution (choke-points where
J is most elevated, aside - uniform J is constant /
uniform-ish material drift).

But tungsten plugs are hard migration barriers so
what you see there is, material accumulates at the
"upstream" side and "wanders away" from the
downstream of current flow. You can see worse
EM outcomes from equal interconnect-plane
material properties, using W plug vias.

Not to mention that the plugs are nasty little heaters
that locally raise interconnect temp (the prime
accelerant) and can torpedo your current capacity
(rules, not facts) if analysis fails to comprehend /
account for / put to lifetime model at stress-temp
and stress-self-heating.

Of course by the time a designer sees the rules, all
of this has long since been "blessed" and any effort
to check work will meet resistance (heh). Believe me,
I have gone down that road (finding and fixing bad
electromigration test conduct and analysis and the
clowns who made it so) more than once.

Thank you so much for your detailed response. I learned a lot of new things.