Is it required for Input to be registered in verilog

[vlsi_maniac]

hi,i have a doubt regarding registered outputs and inputs.
why is output registered and why is that input is needed not be registered in modules (input is registered in test benches)

thanks

 

[bapodradhairyab]

your output will be connected to next module when you will going to make huge system... so to make your output synchronous with clock they are registered...

And inputs are registered if application is such and we need to make them synchronous with clock inside our module...

but majorly registering output gives synchronization as well as removal of glitch if it comes. (exception glitch occur at active edge of clock...

hope you are clear with doubt...

Added after 8 minutes:

and now why input is registered in testbench???
as you are testing any module you need to give input to it and to make input constant you need to make it stored... that's why inputs are defined as reg in test benches...
and output as wire because you need to see what ever coming from module (unit under test) is correct or not so you dont touch it...

for this you should study some books or basic things...

simply just think you had made one design you want to check it ...
how you will test it??? ( you need to create inputs and check outputs accordingly)

how you can generate inputs in verilog? you can define a reg and change its value time by time... that's why in testbenches inputs defined as reg

if you had study electronics circuit subject to check amplifier behaviour or diode rectifier what you was doing???
giving input for that you are using source of voltage (function generator or dc supply)

similarly here in digital you are using reg with changing value...

and for taking output do you need voltage source you need just DMM or Oscilloscope... for that purpose you simulation tool generates wavefrom... thats why no need to define outputs as reg...