Not sure about "softcheck" but electrical rules checks are checking not
connectivity match, but connectivity against other constraints (fanout
maybe, shorted outputs probably, polarity perhaps...). Just because
you drew it (layout) the way you said you were going to draw it
(schematic) has only some bearing on whether you did the right thing,
entirely right.
And of course if you leave things like placement, addition of buffer
stages and branches and so on up to the computer, it might very
well make sub-ideal decisions, maybe even violations - especially
if there is not "closure" between ERCs and constraints (or whatever
the cool kids call what direction you give the auto-layout, these days).
Reading the rules deck, or maybe just its inline comments, ought to
tell you what's possible to fail; your judgment and understanding
of the design and your methods then ought to suggest likely violations.