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early power analysis
before your are going ran IR drop and EM in vstrom tool from cadence
1..In you design where the std.cells are placed close to each other or logic is placed only one side of core area,it causes IR drop issue
2..where you have seen long net ,it causes EM migration issue
after ran the IR drop and EM
where you have seen red hotspot in core area,it's seems IR drop in that area...
where you have seen more congestion in core area..,it causes IR drop
Hi,
Thanks for your reply.
I have a few more questions:
1. Can i run the analysis with SOC Encounter? or i have to use vstorm?
2. How do i run it from Encounter?
1.power pin locations of both VCC and GND (VCC.pp) (GND.pp)
2.bump files/bump lef
3. cl files of macros/std.cells and technololgy files
4.sdc (for twf file)
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