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The dynamic IR drop can affect timing as if the number of switching nets at once increases, so does the probability of voltage drop. This drop can lower the drive capability of gates, thereby increasing the gate delay. remember the value provided by foundry is in percent, so the unit is not relevent here. There are efficient tools for IR drop analysis like Voltus of cadence you can use them to inspect to hot-spot in your design and also you can follow some guideline to lower the drop.
A timing model will be based in part on an expected / allowed
supply tolerance band. The rail span compression will add
(subtract) to (from) that. Presumably your limits are consistent
with the timing models' derivation. But I would want to verify
that, because a timing model based on -5% supply at the pin
(like you'd see on an incoming design-to spec) may fail to
predict the slowness of -5% with another -12% on top. Just
maybe. And you can't trust CAD people to understand all the
layers of design detail that concern you. I've seen some folks
go from chip design into CAD (especially when their product
designs didn't work out so well) but also a lot of pure software
types who you wouldn't trust to grab the right end of a hot
soldering iron. And everything you get from them has passed
through at least two stages of management filter. One of which,
is trying hard to figure out how to get hired by the vendor and
the other, a luckless middle manager.
I'd imagine that an "IR drop" analysis would be pretty dependent
on topology and your exercising, of the circuitry depending from
those rails. I*R drop will be variable w/ position and activity. The
worst drop may not be in the same place as the highest sensitivity
to timing drag-out.
The main physical mechanism why IR drop affects timing is driver "strength", or resistance - it depends on gate overdrive Vgs=Vg-Vs, and Vs is IR drop, whether it's static or dynamic.
There are many effects and different time scales involved in dynamic IR drop - response time (i.e. series resistance) between current sources and on-chip decoupling capacitors, resistance (between the ports and current sources) and capacitance of power nets, series inductance of power/ground nets, etc.
From a simulation, you can extract the power consumption, then the drop, then annotated the gnd-vdd of the std cell which will derive the timing from the liberty and so you can extract the timing impact.