Not an expert but I hope a few tips below help:
1. check if the violation is of a valid path. For example: is the start & end clocks (also clock edges) proper? is this path functionally valid? This requires front end or RTL or functional knowledge towards the design.
2. check clock skew. Make sure it is within your acceptable range.
3. check whether the path has large transition time. Large transition time commonly caused by long net without buffer, and it will badly affect the setup time.
4. check whether the path contains excessive/big buffers.
Also, pls check if the violations at very huge scale with huge slacks? (e.g: multiple violations with slack of few ns each) If yes, you might want to double check high-level root cause, such as clock skew (clock implementation), constraint setting, P&R setting, etc. Else you may investigate at individual path level.