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... but for any synchronous designs NON-BLOCKING assignements to be used to avoid the difference between post synthesis and simulation difference.
-paulki
Do you have any example where using blocking assignment will cause difference between post synthesis simulation?
What would be the value of B when A is 1 at (posedge of clk)
always @ (posedge clk)
b = a;
always @ (posedge clk)
b <= a;
What would be the value of B when A is 1 at (posedge of clk)
always @ (posedge clk)
b = a;
always @ (posedge clk)
b <= a;
It's not invalidated, if the blocking statements are followed by respectively mixed with non-blocking ones. According to the "two step" nature of non-blocking (see 9.2.2), the RHS for each one will be evaluated according to their order in the sequential block, but the LHS will be assigned at the update event (the end of the delta timestep). The hardware equivalent is having combinational logic for the blocking assignments and registers for the non-blocking.9.2.1 Blocking procedural assignments
A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1). A blocking procedural assignment statement shall not prevent the execution of statements that follow it in a parallel block (see 9.8.2).