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I'm designing a digital system in Verilog HDL. The system initially needs to do three tasks individually at each rise edge of the system clock, CLK. In other words, at first rising edge of CLK work 1 is to be done, at second edge work 2, and finally at the third edge work 3 must be done. This only happens once and at the system startup time. My idea is to use the following code but I don't know if that is synthesizable by hardware. If not, what solution do you suggest?
reg FLAG=1; always @(posedge CLK) begin if (FLAG) begin /* do work 1 here */ @(posedge CLK); /* do work 2 here */ @(posedge CLK); /* do work 3 here */ FLAG = 0; end end