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Is @ inside always block synthesizable? (Verilog)

dirac16

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I'm designing a digital system in Verilog HDL. The system initially needs to do three tasks individually at each rise edge of the system clock, CLK. In other words, at first rising edge of CLK work 1 is to be done, at second edge work 2, and finally at the third edge work 3 must be done. This only happens once and at the system startup time. My idea is to use the following code but I don't know if that is synthesizable by hardware. If not, what solution do you suggest?

My idea:

Code:
reg FLAG=1;
always @(posedge CLK) begin
   if (FLAG) begin
      /* do work 1 here */
      @(posedge CLK);
      /* do work 2 here */
      @(posedge CLK);
      /* do work 3 here */
      
      FLAG = 0;
      end
end
 

danadakk

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Not a Verilog expert but seems to me you need to count clock edges and
then decode the state of that 2 bit divide by 3 cntr ? And that state used
to invoke the task needed for that N'th clock edge.

Code:
module 2_bit_Count(
    input clock, reset,
    output [1:0]dout
    );
reg [1:0]dout;
initial dout = 0;
 
always @ (posedge (clock))
   begin
        if (reset)
            dout <= 0;
        else
            dout <= dout + 1;
   end
endmodule

Just add the state reset on 3 and the needed if statements to test count state
for task trigger.


Regards, Dana.
 

FvM

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No, nested always blocks are not synthesizable. You are basically designing a state machine that is only executing once after reset. Use a case construct to select the respective "work" code and stop increasing the state variable in a final hold state.
 

dirac16

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Not a Verilog expert but seems to me you need to count clock edges and
then decode the state of that 2 bit divide by 3 cntr ? And that state used
to invoke the task needed for that N'th clock edge.

Code:
module 2_bit_Count(
    input clock, reset,
    output [1:0]dout
    );
reg [1:0]dout;
initial dout = 0;
 
always @ (posedge (clock))
   begin
        if (reset)
            dout <= 0;
        else
            dout <= dout + 1;
   end
endmodule

Just add the state reset on 3 and the needed if statements to test count state
for task trigger.


Regards, Dana.
Thank you! That is what I was also thinking of.
--- Updated ---

No, nested always blocks are not synthesizable. You are basically designing a state machine that is only executing once after reset. Use a case construct to select the respective "work" code and stop increasing the state variable in a final hold state.
Yeah, I got it! Thank you for your answer.
 

dave_59

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No, nested always blocks are not synthesizable. You are basically designing a state machine that is only executing once after reset. Use a case construct to select the respective "work" code and stop increasing the state variable in a final hold state.
At the risk of being pedantic, this is not a nested always block, it is an always block with multiple clock edges. It is synthesizable, but not by tools you may be familiar with. There was a big push for "behavioral" synthesis about 20 years ago, but it never caught on.
 

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