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Interview Questions: 2 Always Block

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kunal1514

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What would be the value of B when A is 1 at (posedge of clk)

always @ (posedge clk)
b = a;

always @ (posedge clk)
b <= a;
 

ebuddy

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These 2 statements are equivalent if they are the only one in their always block. Assume A is 1 before posedge clk and does not change right away after posedge clk, in both cases, B is 1.
 

paulki

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The question would be more to the coding approach.
As per the code, both the always block are with "posedge clk", that means its presumed to be a sequential circuit which should be coded as per guidelnes as "NON-BLOCKING" assignment statement, in the second always block. Both the code will be providing result B=1, but for any synchronous designs NON-BLOCKING assignements to be used to avoid the difference between post synthesis and simulation difference.

-paulki
 

ebuddy

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... but for any synchronous designs NON-BLOCKING assignements to be used to avoid the difference between post synthesis and simulation difference.

-paulki

Do you have any example where using blocking assignment will cause difference between post synthesis simulation?
 

FvM

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Do you have any example where using blocking assignment will cause difference between post synthesis simulation?

They are discussed e.g. in the classical cummings paper: https://www.edaboard.com/threads/175727/

Generally, it can be expected in those cases, where schedule of block execution matters. So you must have at least two blocks in your design to see an effect. Inside a block, the behaviour won't change.

My suggestion would be slightly different, to cover also those cases, where blocking statements are reaonable in synchronous blocks: Use non-blocking statements for the final assignments to registered variables and (if required) blocking statements for intermediate results that have to be calculated before, in the same clock cycle.

A text book would possibly suggest to place these preceding calculations in a separate combinational block. But I think, code readabilty will be affected.
 
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koppolu1981

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What would be the value of B when A is 1 at (posedge of clk)

always @ (posedge clk)
b = a;

always @ (posedge clk)
b <= a;

Hi.
If these two always blocks are considered sseperately for the behaviour analysis, then both doesn't have any difference w.r.t simulation. But for synthesis using blocking statement for modelling a flop/register element is not a good coding practice.

If we put these two statements in the same module, then this would result in a multple drivers error for synthesis. For simulation it doesn't make any difference. The value of b is 1 in both cases @( posedge clk).
 

dnk0904

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What would be the value of B when A is 1 at (posedge of clk)

always @ (posedge clk)
b = a;

always @ (posedge clk)
b <= a;

This situation can be same between 2 block if you synthesize and simulate, I think that. But if you write "a = b" , you maybe thought wrong or confuse between two kind of procedure assignment.

I think you should read more about two kind of procedure assignment to present wrong design.

MODERATOR ACTION: signature link removedMODERATOR ACTION: MODERATOR ACTION:
 

phoenixpavan

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Hi Kunal,
the first procedural assignment b=a is a blocking statement, so all the statements that come after this will be executed "only" after "a" is assigned to "b". So it blocks all other statements within the always block from being executed until the execution of this step is complete.

the second procedural statement b<=a is a non-blocking assignment, so it "does not" block the next statements from being executed i.e it allows for concurrent execution of the statements in a always block. Infact because of this concurrency feature HDL have an advantage over programming languages where sequential execution of statements is the norm.

These non-blocking statements are essential when coding sequential circuits where complementary outputs must be available in the same time.
 

ebuddy

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How do you guys code it when you need to design sequential logic and the input of the register is driven by complex combination logic?

Let me have an example:

//complex logic.
aways (*) begin
...
...
.. 20 lines ..
...
a = ...
end

always @ (posedge clk)
b <= a;

Is there a way to combine the above 2 processes into 1 process?
 

FvM

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I already answered the question. You can place the non-registered preprocessing into the synchronous always block by using blocking assignments. As long as the intermediate results aren't used outside the always block, there's no risk to create race conditions and simulation mismatch.

I'm mostly writing VHDL, and there you have the variable assignment := that behaves similar to the Verilog blocking =. Because it's local to the process,
some pitfalls of blocking assignments in Verilog are avoided with VHDL variables.
 

ebuddy

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Well, there has been a rule in Verilog saying don't use blocking and non-blocking statements in the same process. I believe the language LRM says it in a slightly different way. It says the order that blocking and non blocking statements get executed is undefined.

In order to use blocking statements to get the intermediate result, and then assign it to the register by non-blocking (like VHDL does), it assumes that blocking statements get executed first, followed by non-blocking statement. This is not guaranteed though, even if the blocking statements are placed in the code before non-blocking statements.
 

FvM

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I don't agree. Can you please point to the respective paragraph in the Verilog specification or a tools manual? I'm not too familiar with Verilog coding, but I have used the said combination in Verilog, and it always worked as intended. Of course you can't mix blocking and non-blocking arbitrarily, you have to consider what's their effect.

P.S.: The basic rule for blocking assigments says:
9.2.1 Blocking procedural assignments
A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1). A blocking procedural assignment statement shall not prevent the execution of statements that follow it in a parallel block (see 9.8.2).
It's not invalidated, if the blocking statements are followed by respectively mixed with non-blocking ones. According to the "two step" nature of non-blocking (see 9.2.2), the RHS for each one will be evaluated according to their order in the sequential block, but the LHS will be assigned at the update event (the end of the delta timestep). The hardware equivalent is having combinational logic for the blocking assignments and registers for the non-blocking.
 
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