Do you mean assertion and coverage checking?
Ya I told them that, But they want me to give some test vectors and check, which will provide maximum coverage i guess.
They asked me to develop a test plan to test the circuitry.
In that case can you help me with the test vectors that will provide maximum coverage...
Different test vectors can be created using variables required as random and than post randomize the thing. The different number of transaction can be give in the test cases
First, create a test that exhaustively checks the 16 bit adder. Since the 16bit adder increments, you only need 64k cycles to verify it. Second, create a test that passes carry from lower 16bits to upper 16bits.
So, one test vector for 16bit adder verifications, and a few more for the whole 256 bit incrementor.