Interconnect Delay Vs Clock Period

[Varun124]

Hi Guys,

I have one doubt in interconnect delay and clock period. In my design I have a clock source and it reached to an inverter. The interconnect delay b/w inverter output and next nand gate input is more than clock period i.e. interconnect delay = 5.029ns and clock period = 4ns . In this case does the clock will escape ?

Thanks in Advance

 

[ThisIsNotSam]

this is one very slow inverter, damn. you could do a simple spice analysis to be sure... or redesign and avoid the problem completely.

 

[vaibhava]

Hi Guys,

I have one doubt in interconnect delay and clock period. In my design I have a clock source and it reached to an inverter. The interconnect delay b/w inverter output and next nand gate input is more than clock period i.e. interconnect delay = 5.029ns and clock period = 4ns . In this case does the clock will escape ?

Thanks in Advance

Hello Varun,

can you please clarify on "does the clock will escape ?"

Moreover what is the design intent and the tool being used?

Best,
vaibhava

 

[dick_freebird]

5nS delay just from the interconnect? I have never seen
that kind of loading in logic. Perhaps it's just a terribly
bad routing, or perhaps the line capacitance is mis-
extracted or mis-transcribed?

It is unclear where the next registered stage is, in this
circuit. Delay > period is going to be a timing hazard
that depends on PVT (expect low temp fast, to be OK
and high temp, slow, not - so your circuit would be
"environmentally unreliable" in its behavior. Skip a
cycle or catch bad data starting somewhere in the
middle.

I'd look at the timing model and input validity first,
and see what accounts for the ridiculous loading.