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Interconnect Delay Vs Clock Period

Varun124

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Hi Guys,

I have one doubt in interconnect delay and clock period. In my design I have a clock source and it reached to an inverter. The interconnect delay b/w inverter output and next nand gate input is more than clock period i.e. interconnect delay = 5.029ns and clock period = 4ns . In this case does the clock will escape ?

Thanks in Advance
 

ThisIsNotSam

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this is one very slow inverter, damn. you could do a simple spice analysis to be sure... or redesign and avoid the problem completely.
 

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