Integer multiplication

[RAVI30]

Hi....
i am need to use integer multiplication in my design both are integers only... but while simulating the multiplication result is coming as zero.......

my design is as folloes
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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
architecture arch of bch_syndrome is
    signal e1:std_logic_vector(15 downto 0);
    signal b1:std_logic_vector(15 downto 0);
    signal c1:integer;--unsigned(15 downto 0);
    signal f1:integer range 0 to 65536;
    signal d1:integer;--unsigned(31 downto 0);
    signal syndromesum1:integer; 
    signal i1:integer range 0 to 65535;
    signal j1:integer range 0 to 32400;
 
begin 
process(reset,clk,count)
    variable a1:std_logic_vector(15 downto 0);
    begin
      if(clk'event and clk= '1') then
      if(reset='1')then
        i1<=0;
        j1<=32400;
        b1<=(others=>'0');
        c1<=0;
        d1<=0;
        a1:=(others=>'0');
        e1<=(others=>'0');
        syndromesum1<=0;
else
           e1<=(e1(14 downto 0)& DataIn1(j1));
            b1<=a1 xor e1;
            c1<= conv_INTEGER(b1);
            f1<= alpha_value(i1);
            d1<=f1*c1;
            syndromesum1<=syndromesum1+d1;
            a1:=conv_STD_LOGIC_VECTOR(d1, 16);                                               
            d1<=0;
            j1<=j1-1;
        end if;
        end if;
    end process;

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plz help me to solve this problem

 

[TrickyDicky]

Did you assert reset at the start of the sim? Have you checked the previous signals in the pipeline?

 

[RAVI30]

Sorry i didn't got ur point....

 

[TrickyDicky]

Does you testbench assert reset at the start of the sim to make sure all the signals are in a known state? Have you looked at all the signals on the waveform to see where the problem is coming from?

 

[Paxwell]

Signals are assigned the new value at the end process, which in your case means that d1 will always be zero, since you assign 0 to d1 at the end. Start by removing the line d1 <= 0 and go from there.

 

[K-J]

e1<=(e1(14 downto 0)& DataIn1(j1));
b1<=a1 xor e1;
c1<= conv_INTEGER(b1);
f1<= alpha_value(i1);
d1<=f1*c1

Looking at the above snippet of code leads me to believe that you think these signal assignment statements will update immediately since each statement depends on the immediately preceding line and because you're asking a very basic question so you probably don't have much experience with VHDL yet. It could be that you do mean to have this pipelined as you've written it, but I'm guessing not.

If you are expecting things to update immediately (i.e. after the assignment to 'e1', that new value is used then the next line which is an assignment to 'b1' that uses 'e1') then you need to change all of your signals to variables and use variable assignments only outputting the final result as a signal.

Your best bet though is to start up the simulator and step through the code. Debugging through a forum is not very efficient.

Kevin Jennings

 

[RAVI30]

Thank you so much to every one.....