angk
Newbie level 3
Hello,
This is my first post in this forum. I have read many other related posts about my problem, but I couldn't come to a conclusion so I decided to start a new thread.
In one stage of my project I need to divide two signed integers and extract a signed integer result.
My main concern is that this is a video processing project and I think that a 32 cycles pipelined divider won't work properly and fast.
Assuming a frame rate of 30 fps and a frame resolution of 320x240=76800 pixels per frame.
The division has to be done for every single pixel of the frame, so I need to find the optimal way to do it.
Can someone suggest which way would be optimal for my division ?
I need the VHDL code to be synthesizable and I am still not sure whether the (/) operator will work.
Thanks![Smile :) :)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
This is my first post in this forum. I have read many other related posts about my problem, but I couldn't come to a conclusion so I decided to start a new thread.
In one stage of my project I need to divide two signed integers and extract a signed integer result.
My main concern is that this is a video processing project and I think that a 32 cycles pipelined divider won't work properly and fast.
Assuming a frame rate of 30 fps and a frame resolution of 320x240=76800 pixels per frame.
The division has to be done for every single pixel of the frame, so I need to find the optimal way to do it.
Can someone suggest which way would be optimal for my division ?
I need the VHDL code to be synthesizable and I am still not sure whether the (/) operator will work.
Thanks