Integer division for video processing project.

[angk]

Hello,
This is my first post in this forum. I have read many other related posts about my problem, but I couldn't come to a conclusion so I decided to start a new thread.

In one stage of my project I need to divide two signed integers and extract a signed integer result.

My main concern is that this is a video processing project and I think that a 32 cycles pipelined divider won't work properly and fast.

Assuming a frame rate of 30 fps and a frame resolution of 320x240=76800 pixels per frame.
The division has to be done for every single pixel of the frame, so I need to find the optimal way to do it.

Can someone suggest which way would be optimal for my division ?

I need the VHDL code to be synthesizable and I am still not sure whether the (/) operator will work.

Thanks

 

[barry]

I don't see any reason a pipelined divider CAN'T work; regardless of the number of cycles, you can still get one division per clock cycle. For your application you need to do 2.3E6 divisions/sec, perfectly doable with even a single divider. Depending on your device, you can do multiple divisions in parallel.

It's hard to tell what an "optimal" solution is, when you give us very few details. I'd suggest you get the most expensive FPGA you can afford, one with lots of DSP blocks.

 

[angk]

I don't see any reason a pipelined divider CAN'T work; regardless of the number of cycles, you can still get one division per clock cycle. For your application you need to do 2.3E6 divisions/sec, perfectly doable with even a single divider. Depending on your device, you can do multiple divisions in parallel.

It's hard to tell what an "optimal" solution is, when you give us very few details. I'd suggest you get the most expensive FPGA you can afford, one with lots of DSP blocks.

The project is for academical purposes, so the available board provided is an Altera DE2-115.
I 've read in the forum people suggesting using the Megafunction IP Core.
Do you think this would be the optimal in terms of speed-efficiency and throughput ?

 

[barry]

That device has a lot of multipliers, it will probably work depending on what ELSE the device needs to do...

 

[angk]

That device has a lot of multipliers, it will probably work depending on what ELSE the device needs to do...

Thanks for the reply. I will keep you updated, if I meet any difficulties during my progress.

 

[FvM]

Although 2.3 MHz will probably work without pipelining, depending on the bit length which hasn't been mentioned, a pipelined design gives you more flexibility. This means you should use an Altera divider Megafunction instead a "/" operator.

 

[TrickyDicky]

What is the reason you cant afford to insert a few clock delay into the video pipeline? what are you trying to do?
Video processing is often done with pipelines. You can usally add as much latency as you like in most situations. Diffculty arrises if you have to stay in sync with the video itself. What are you trying to do/