instantiating a module inside an always block

[yupina-chan]

hi. can i instantiate a module inside an always block?
what i want to do is save values to a line buffer. i only want to execute my line buffer only at a certain period of time so inside my always block(at positive clock edge the values enter), i have a counter. whenever the counter reaches the specified count, it performs the line buffer module. how can i make this in verilog? thanks in advance

 

[TrickyDicky]

A module doesnt get "executed" or "performed", it gets instantiated. So it cannot be instantiated inside an always block. Instantiating a module is like placing a chip on a circuit board, and you wouldnt want to add or remove chips based on certain conditions during run-time.

 

[yupina-chan]

so how can i get over with this problem? like how can i save the entered values at a certain period of time?
example: only the values entered at 20<count<40 is saved but the input is still streaming

 

[TrickyDicky]

create a write enable.

 

[yupina-chan]

thanks for the reply. in what module should i create the write enable? can you elaborate further please?

 

[TrickyDicky]

You need to create it so that it connects to the write enable of the memory. So creating at the same level as the counter would be sensible, as you can easily do the compare there.