verilog pad insertion
Hi,
I would say this is purely requirement based.
Say for example, not all your macros have their locations prior hand and if you would like to place these macros based on shortest connection to IO pads; it is good to have then introduced prior to starting to floorplan
If there are timing paths starting from pad and if you would like to accurately mimic the length of wire from pad to the cells connecting to it, it is then a must to have the paths.
Also for a design, where not all your pad locations are known prior hand and where you would like the tool to make a choice of location, it is good to have these pads instantiated just before placement.
For example, if you are planning to use DC-Topographical to optimize your design, based on default floorplan, you could insert them well ahead in RTL netlist or Gate level initial netlist.
If there is no requirement based on pad location and all the other placement details of the design is totally independent of the Pads, then you could insert them at last.
However, atleast VDD and VSS pads need to be present during Floorplanning stage to take care of IR drop analysis. Anyway, we would be creating these VDD/VSS pads only in ICC and it will definitely be not ther in DC dumped netlist.
Just my 2 cents!
Thanks,
Daman