Insert I/O PAD before or after DC

[gaom9]

i/o pad

Hi, everybody
I am sorry to ask such a simple question here.
I want to know should we insert the I/O PAD before or after the DC when synthesis?
In other word, should we insert the I/O in the RTL code before importing it to DC, or should we insert the PAD in the output gate-code from DC after synthesis?
I think if we insert PAD in RTL, DC will consider the delay and other effect of the PAD in synthesis to make a better result, is that right?
Because the new version DC does not support the insert_pad command, I read some topic about this, and it tells that we just insert PAD through rewrite the code "Do not automatically insert pad use DC, do it by yourself!!!", is that right or is there any other method?
If we should insert the PAD not automatically, I think we will easily get a mistake when the NO. of PADs are too large.

Can anyone give me some advice, please?

Thank you!
Best regards!

 

[jbeniston]

insert i/o

I've worked on designs where synthesis is done with pads and without. Timing analysis will be more accurate if the pad is there.

If you want to include pads, just instantiate them in your Verilog/VHDL.

 

[gaom9]

io pad

===============
Hi Gaom9





IO pads are placed at the very final stage of the design, since these actually nver effect the timings. IO pads just act as medium to connect the IO pins to the external world. So u can insert these Pads even after metal fill and decaps at back end.

u can write a small tcl scripts to insert IO pads. Ask the back end engineers if they have these scripst ready.



Hope t his helped you



Best regards



Suresh
===============

 

[ngvanbinh2000]

automatic insert pad

hi ban!
DE chen io pad ban viet file top level cua design roi chen io pad trong file do(chen truoc khi tong hop DC).Khi tong hop DC ban set don't touch cac io pad co nhu the thi phan P&R se co cac thong tin ve io pad de thucj hien P&R
Regards!

 

[HolySaint]

synthesis insert pad cells

hi ban!
DE chen io pad ban viet file top level cua design roi chen io pad trong file do(chen truoc khi tong hop DC).Khi tong hop DC ban set don't touch cac io pad co nhu the thi phan P&R se co cac thong tin ve io pad de thucj hien P&R
Regards!

I cannt read clearly with so many short words

=.=

 

[daman]

verilog pad insertion

Hi,

I would say this is purely requirement based.

Say for example, not all your macros have their locations prior hand and if you would like to place these macros based on shortest connection to IO pads; it is good to have then introduced prior to starting to floorplan

If there are timing paths starting from pad and if you would like to accurately mimic the length of wire from pad to the cells connecting to it, it is then a must to have the paths.

Also for a design, where not all your pad locations are known prior hand and where you would like the tool to make a choice of location, it is good to have these pads instantiated just before placement.

For example, if you are planning to use DC-Topographical to optimize your design, based on default floorplan, you could insert them well ahead in RTL netlist or Gate level initial netlist.

If there is no requirement based on pad location and all the other placement details of the design is totally independent of the Pads, then you could insert them at last.

However, atleast VDD and VSS pads need to be present during Floorplanning stage to take care of IR drop analysis. Anyway, we would be creating these VDD/VSS pads only in ICC and it will definitely be not ther in DC dumped netlist.
Just my 2 cents!

Thanks,
Daman

 

[sunilbudumuru]

how to write a io pad file in verilog

Hi Friends,

Pads can be inserted during the DC(Older version) synthesis phase itself. But the current versions (for ASICflow) doesn't support insertion of PADs to the toplevel design with the following script flow. I guess, 2004 version of DC tool can insert the PADs with the following script flow.

########################################
current_design <top_desogn>
...
...
set_port_is_pad [get_ports *]

/////PADs to be Inserted from the library ////
remove_attribute [get_lib_cells LIBRARY/<PAD_TO_BE_INSERTED>] dont_touch

remove_attribute [get_lib_cells LIBRARY/<PAD_TO_BE_INSERTED>] dont_use

////// Can select the exact PADs from library to the required ports /////

set_pad_type -exact PAD_TO_BE_INSERTED [list <PORTS>]

insert_pads

change_names ..

write -f verilog -h -o <output_netlist>
###########################


But, we have to be sure and match the exact PADs from the library. In the above flow, if you dont give set_pad_type -exact PAD_TO_BE_INSERTED [list <PORTS>],
then the tool will select automatically the proper PAD that matches to the port.
But it is advisable to mention the exact PAD to be selected for a pirticular port.

Hope this helps !!!!

(If ur DC supports FPGA flow (DC FPGA, I guess the above script will work))

Cheers !!!


Sunil Budumuru
asic-dft.com

 

[eeeng]

Re: insert i/o

I've worked on designs where synthesis is done with pads and without. Timing analysis will be more accurate if the pad is there.

If you want to include pads, just instantiate them in your Verilog/VHDL.

Hi...
I'm working on the whole cadence flow...I want to include the pads in the code using RTL Compiler ...Could you guide me to do that ?

Thanks in advance