int19
Newbie level 6
Hi all.
I have made a VHDL testbench to simulate a post layout netlist. The module I need to simulate doensn't have IN ports but only INOUT ports. So when I try to assign a value to any of these inout ports nothing happens, values all remain undefined.
What should I do?
Thanks.
I have made a VHDL testbench to simulate a post layout netlist. The module I need to simulate doensn't have IN ports but only INOUT ports. So when I try to assign a value to any of these inout ports nothing happens, values all remain undefined.
What should I do?
Thanks.
