Information about SystemVerilog

[zhangpengyu]

about verification

Hi
guys!

I study specam e now.And I want to know that will systemverilog replace
e.
Does systemverilog base on verilog and adds features to verilog?Does it contain open vera?
What is systemverilog?

Thanks!


zhpy

 

[linuxluo]

Re: about verification

hi,
As I know, first systemverilog is based on e and verilog, but after some debate between synopsys and cadence or other, now systemverilog also include openvera.
as for e, I think it's hard to learn but powerful , and it dominate the market of HVL. So it will not die in years.

 

[zhangpengyu]

about verification

Hi
Is it true that systemverilog is based on e and verilog;I heard that systemverilog is the product of synopsys,it's used to compete against e!

zhpy

 

[linuxluo]

Re: about verification

hi,
I think several years after, there will exist just systemverilog and systemc.

 

[zhangpengyu]

Re: about verification

SystemC will die!
E will stand for many years!
Systemverilog will progress in the future!

zhpy

 

[AlexWan]

Re: about verification

For my opinion Verilog is enough for verification.
In IEEE 1364-2001, behavior verilog is very powerful.
SystemC and SystemVerilog are higher level languages. During some basic operations, they are difficulty.

 

[archer]

Re: about verification

Who knows!
At first both Synopsys and Cadence claimed supporting System C, now Synopsys turned to System Verilog. Even though,Verilog 2005 and System Verilog 3.1 may be accepted by two different standard groups. Oops! Till today, there is no unified data model and database embraced by the whole industry. Cooperation is really needed between EDA vendors.

 

[masai_mara]

Re: about verification

I think what has been said above is pretty accurate and system verilog has borrowed from e and open vera but also extensively from C. so its going to be a very powerful tool for assertion based verification and also quite succintly express RTL designs. But it still has to settle down with good eda support and issue of double standards with verilog 2005.

 

[nagraj]

Re: about verification

SystemVerilog is a competator of VERA,e and SystemC .....!!!!!!!!!

 

[Memphis]

about verification

I am also the supporter of system Verilog, though I am not familier enough... I am also the user of verilog now... I think learning system verilog should be more easiler than system C for me..

 

[maxsnail]

Re: about verification

System verilog , how many tools support it now. it only show a picture for you now.
but systemc can work well now in cadence IUS platform.
I always hear learn C or systemc is a hard thing, really???? learn a language is too hard???? I can not agree, now e is Cadence, how it will going, I think some methodology will move to SystemC

 

[rprince006]

Re: about verification

I don't know much about system-verilog, but it seems that system-verilog adopted
many features from C and verilog. Suppose system-verilog has also adopted many features from vera and e, it should be very powerful, but very difficult to learn (e is difficult to learn too) as well. I cannot imagine that!

 

[gogogo]

about verification

system verilog now is not widely used, who know its future?
these languages depend on the support of eda software

 

[andromeda]

about verification

If we are talking about system level design, SW/HW co-design, co-verification, partitioning, Architecture level iteration: the only language usefull in this areas is SystemC.
For verification, I also strongly prefer SystemC over e, Vera, SystemVerilog or good old HDLs. It allows you continuity with pure C++ and SystemC models (with repalcement of only 1 module with Verilog model). Notice that Verilog-SystemC co-simulation works perfectly today with nc-verilog an nc-systemc.
In the world of contraint-random verification, SystemC alone give you ability to build whatever you want (of course it is much easier with built-in features in Specman, but Specman licenses are expencive).
It looks to me that SystemVerilog will kill old HDLs, Vera and e, but SystemC will survive (target of this language is different).
Design will be done in SystemVerilog, System level modeling and Architecture explaration will be SystemC world and verification will be in any of those 2 remaining languages, depending on preferences, tool support.

 

[Kulprashant]

about verification

hi,
it will happen in future.systemverilog and systemc having good futures.

with regards,
kul.

 

[Prasanna Kumar]

Re: about verification

it all depends on EDA tools, System C as a verification language is the good, but as a designing lanuage in the future depends on any EDA tool Vendor who can Synthesize the system C design.

HDL's are the BEST and are the reference to any new convention.

 

[jjww110]

about verification

use System C for model
use systemverilog for design and verification

 

[spauls]

Re: about verification

System C is best for H/W and S/w coverificationa nd architecture modelling.