about verification
If we are talking about system level design, SW/HW co-design, co-verification, partitioning, Architecture level iteration: the only language usefull in this areas is SystemC.
For verification, I also strongly prefer SystemC over e, Vera, SystemVerilog or good old HDLs. It allows you continuity with pure C++ and SystemC models (with repalcement of only 1 module with Verilog model). Notice that Verilog-SystemC co-simulation works perfectly today with nc-verilog an nc-systemc.
In the world of contraint-random verification, SystemC alone give you ability to build whatever you want (of course it is much easier with built-in features in Specman, but Specman licenses are expencive).
It looks to me that SystemVerilog will kill old HDLs, Vera and e, but SystemC will survive (target of this language is different).
Design will be done in SystemVerilog, System level modeling and Architecture explaration will be SystemC world and verification will be in any of those 2 remaining languages, depending on preferences, tool support.