Information about designing IO pads

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eecs4ever

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Hi ,

I am planning to design some pads in 0.18 um TSMC CL018 HV.

Pad types that i need:
VDD PADS, GND PADS, Digital I/O, Analog In , Analog Out pads, High Voltage Pads.

Does any one have some design guides or documents that you can share with me ?

Any advice is also appreciated. This is for a research chip, so ESD is going to be minimal.

Thanks!
 

Re: IO Pad Designs

TSMC supply free of charge IO libs for customers. IO desig rules are inside TSMC's DR document
 

Re: IO Pad Designs

I'm looking for more general IO design guidelines.

+ TSMC won't give me any IO pads since I'm not a customer.
 

Re: IO Pad Designs

If ESD protection isn't a big issue, you can use simplest way to IO design:
1) VDD PADS, High Voltage Pads - use big (W>=600um, L>=0.5um) grounded gate NMOSFET with drain ballasting, drown in accordance to TSMC's DR; If HV means >5V, then use RESURF NMOSFET (Nwell drain, L>0.8um,...).
2) Analog In , Analog Out pads - use structure as in 1) plus secondary protection from 100 Ohm N+ or POLY resistor and 20um grounded gate NFET (L~0.4um);
3) Digital I/O - driver PFET and NFET in accordance to TSMC's DR (guard rings,...), the rest part - into P+ guard ring region in free form.
 
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