In what situation Design Compiler will synthesis RTL into latch?

[hfooo1]

in waht situation Design Compiler will synthesis RTL into latch?

someone said we dont use latch because of DFT problem.
But can we solve it by adding a MUX before it?

 

[Nandy]

latch

always @(a or b)
if(a) out = 1'b1;
else if(b) out = 1'b0;

Latch will be introduced for 'out', since 'else' is missing.

www.nandigits.com
Netlist Debug/ECO in GUI mode

 

[atena]

Re: latch

in waht situation Design Compiler will synthesis RTL into latch?

someone said we dont use latch because of DFT problem.
But can we solve it by adding a MUX before it?

latch will be introduced when you use reg in Verilog (as well as variable in VHDL) associated with output port and store the value arcording to the changing clock level(clk='1'). It's correct for both VHDL and Verilog.

 

[pramodm]

latch

latch will be infered when a combinational circuit described improperly

example:
1. when sensitivity list is not complete i.e all the combinational inputs must in sensitivity list
2. In always or process all the control paths are not evaluate the output