kil
Member level 5
hi alll,
while calculating the clock time period of deign we will cosnider the t setup time and time clock to output delay and combinatioanl delay but why we do not consider the hold time in calculating for time period of a circuit.
what does this hold time refers and what its signficance in design of sequential circits .
where exactly we cosnider the hold time violations.....................................
thanks,
kil
while calculating the clock time period of deign we will cosnider the t setup time and time clock to output delay and combinatioanl delay but why we do not consider the hold time in calculating for time period of a circuit.
what does this hold time refers and what its signficance in design of sequential circits .
where exactly we cosnider the hold time violations.....................................
thanks,
kil